REDUC=0, BIGEND=0, CMDLATR=0
DDR Control Register 28
| CSMAP | Chip Select Map |
| RESERVED | Reserved |
| REDUC | no description available 0 (0): 16-bit - standard operation using full memory bus 1 (1): 8-bit - Memory datapath width is half of the maximum size. The upper half of the memory busses (DQ, DQS, and DM) are unused and relevant data only exists in the lower half of the busses. |
| RESERVED | Reserved |
| BIGEND | Big Endian Enable 0 (0): Little endian 1 (1): Big endian |
| RESERVED | Reserved |
| CMDLATR | Command Latency Reduction Enable 0 (0): Disable 1 (1): Enable |
| RESERVED | Reserved |